RISC-V 64-bit: rework assembly code. - #10893
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Jenkins: retest this please Valgrind |
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Pull request overview
This PR reworks the RISC-V 64-bit crypto acceleration implementation by moving generated RISC-V assembly into standalone .S/helper C files and wiring the core C implementations (AES/SHA/Poly1305/ChaCha) to call the new RISC-V backends. It also updates the build system and configuration logic so autoconf/automake builds compile the new sources consistently (including AES-GCM streaming support).
Changes:
- Replace prior RISC-V C/inline-asm implementations for SHA-256/SHA-3/Poly1305 (and related pieces) with generated standalone assembly plus helper C sources, and add new RISC-V transform hooks in SHA-256/SHA-512 core code.
- Add/adjust public/internal headers for new RISC-V entry points (SHA-256/SHA-512 transforms, AES routines, Poly1305 layout + functions, ChaCha speedup macro).
- Update build/config integration (
include.am,configure.ac) to compile the new RISC-V sources and allowWOLFSSL_AESGCM_STREAMunder RISC-V asm.
Reviewed changes
Copilot reviewed 21 out of 33 changed files in this pull request and generated 3 comments.
Show a summary per file
| File | Description |
|---|---|
| wolfssl/wolfcrypt/sha512.h | Declares RISC-V SHA-512 transform entry points. |
| wolfssl/wolfcrypt/sha256.h | Declares RISC-V SHA-256 transform entry points. |
| wolfssl/wolfcrypt/poly1305.h | Aligns RISC-V Poly1305 struct layout with generic and updates RISC-V function prototypes. |
| wolfssl/wolfcrypt/libwolfssl_sources_asm.h | Ensures generated asm sees consistent feature macros by including options.h in autoconf builds. |
| wolfssl/wolfcrypt/chacha.h | Adds USE_RISCV_CHACHA_SPEEDUP and aligns buffer alignment requirements for RISC-V asm. |
| wolfssl/wolfcrypt/aes.h | Declares RISC-V AES primitives, bulk modes, and AES-GCM helpers. |
| wolfcrypt/src/sha512.c | Enables core SHA-512 code under RISC-V asm and dispatches transforms to RISC-V backends. |
| wolfcrypt/src/sha256.c | Enables core SHA-256 code under RISC-V asm and dispatches transforms to RISC-V backends. |
| wolfcrypt/src/port/riscv64/riscv-64-sha3-asm.S | Adds generated standalone RISC-V SHA-3 assembly implementation. |
| wolfcrypt/src/port/riscv/riscv-64-sha3.c | Removes prior RISC-V SHA-3 C/inline-asm implementation. |
| wolfcrypt/src/port/riscv/riscv-64-sha256.c | Removes prior RISC-V SHA-256 implementation. |
| wolfcrypt/src/port/riscv/riscv-64-poly1305.c | Removes prior RISC-V Poly1305 implementation. |
| wolfcrypt/src/poly1305.c | Routes Poly1305 key/final/block handling through new RISC-V entry points. |
| wolfcrypt/src/chacha.c | Integrates RISC-V ChaCha speedup without excluding the C implementation wholesale. |
| wolfcrypt/src/aes.c | Implements RISC-V AES block/key schedule hooks and adds RISC-V accelerated CBC/CTR/GCM/XTS paths (incl. streaming). |
| src/include.am | Switches automake source lists from old port/riscv C files to new port/riscv64 generated asm sources. |
| configure.ac | Enables AES-GCM streaming under RISC-V asm and adds zba option handling for RISC-V asm builds. |
| .wolfssl_known_macro_extras | Adds WOLFSSL_RISCV_ASM_INLINE as a known macro extra. |
| .github/workflows/codespell.yml | Adds vor to codespell ignore list (assembly mnemonic). |
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Assembly code generated from scripts. Have separate assembly files and new inline code.
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Jenkins: retest this please FIPS ready aborted |
JacobBarthelmeh
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Jul 16, 2026
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Tested the versions I could using QEMU. Sections in generic wolfcrypt/src/*.c files are reviewed and isolated to RISCV builds. Thanks Sean.
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Description
Assembly code generated from scripts.
Have separate assembly files and new inline code.
Testing
Regression tested RISC-V 64-bit.